Communication receivers that recover digital signals must sample an analog waveform and then reliably detect the sampled data. Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. As data rates increase, the receiver must both equalize the channel, to compensate for such corruptions, and detect the encoded signals at increasingly higher clock rates. Decision-feedback equalization (DFE) is a widely used technique for removing intersymbol interference and other noise at high data rates.
Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using, a feedback loop based on previously recovered (or decided) data. In one typical DFE-based receiver implementation, a received analog signal is sampled in response to a data-sampling clock after DFE correction and compared to one or more thresholds to generate the recovered data.
To acquire the correct clock phase and properly sample incoming data signals in the center of the data “eye” opening, a clock and data recovery (CDR) circuit derives the correct clock phase by “locking” onto the eye center or transitions in the incoming data signals. To compensate for jitter in the incoming data signals, the CDR might be implemented as a second-order CDR having a proportional term and an integral term in the transfer function of the CDR. To tailor the transfer function to meet certain requirements (e.g., jitter response) of the application using the CDR, analog CDR implementations rely on the adjustment of component values such as resistances, currents, capacitances, etc. to meet the desired requirements. However, the value of the components are dependent on temperature and operating voltage, and manufacturing process variations might make CDRs made under certain process “corners” incapable of operating with the desired requirements. Digital CDR solutions solve analog shortcomings but meeting jitter requirements can be a challenge at high data rates.